Presentation 2013-01-17
Implementation of a pupil detection method using an FPGA accelerator and a high-level synthesis tool
Keisuke DOHI, Yuichiro SHIBATA, Kiyoshi OGURI,
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Abstract(in English) In this paper, we describe an implementation of a pupil detection using MaxCompiler which is a high-level synthesis framework for FPGA accelerators, and show comparison results with Venlog HDL design in terms of performance and an amount of user description. The MaxCompiler intends to accelerate high-performance computing application using deep-pipelined stream-onented architectures which are generated by a Java-based language. As a result, our design achieved comparable performance with a design described by Verilog HDL while the required amount of the user description was about one-third
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Keyword(in English) High-Level Synthesis / MaxCompiler / FPGA / Pupil detection / Computer Vision
Paper # VLD2012-132,CPSY2012-81,RECONF2012-86
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Committee RECONF
Conference Date 2013/1/9(1days)
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Language JPN
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Title (in English) Implementation of a pupil detection method using an FPGA accelerator and a high-level synthesis tool
Sub Title (in English)
Keyword(1) High-Level Synthesis
Keyword(2) MaxCompiler
Keyword(3) FPGA
Keyword(4) Pupil detection
Keyword(5) Computer Vision
1st Author's Name Keisuke DOHI
1st Author's Affiliation Graduate School of Engineering, Nagasaki University()
2nd Author's Name Yuichiro SHIBATA
2nd Author's Affiliation School of Engineering, Nagasaki University
3rd Author's Name Kiyoshi OGURI
3rd Author's Affiliation School of Engineering, Nagasaki University
Date 2013-01-17
Paper # VLD2012-132,CPSY2012-81,RECONF2012-86
Volume (vol) vol.112
Number (no) 377
Page pp.pp.-
#Pages 6
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