| Presentation | 2013-01-16 Speeding up Multiple Sections of Binary Code by Hardware Accelerator Tightly Coupled with CPU SHUNSUKE Satake, Nagisa ISHIURA, SHIMPEI Tamura, Hiroyuki TOMIYAMA, Hiroyuki KANBARA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This article presents an improvement over the hardware accelerator tightly coupled with a CPU While the previously proposed method assumes only a single fragment from a binary code to be synthesized into an accelerator, our method attempts to accelerate multiple fragments. Instead of connecting multiple acceleratos corresponding to the fragments in parallel, a single hardware module is synthesized which is capable of accelerating the multiple sections. This enables sharing of datapath resources as well as the control among multiple tasks, which makes the accelerator cost-efficient. Furthermore, the capability of handling multiple code fragments makes it possible to synthesize complex control structures, such as calling software subroutines from a hardware accelerator, into hardware. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | embedded systems / hardware/software codesign / hardware accelerator / high-level synthesis |
| Paper # | VLD2012-119,CPSY2012-68,RECONF2012-73 |
| Date of Issue |
| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2013/1/9(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Reconfigurable Systems (RECONF) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Speeding up Multiple Sections of Binary Code by Hardware Accelerator Tightly Coupled with CPU |
| Sub Title (in English) | |
| Keyword(1) | embedded systems |
| Keyword(2) | hardware/software codesign |
| Keyword(3) | hardware accelerator |
| Keyword(4) | high-level synthesis |
| 1st Author's Name | SHUNSUKE Satake |
| 1st Author's Affiliation | Kwansei Gakum University() |
| 2nd Author's Name | Nagisa ISHIURA |
| 2nd Author's Affiliation | Kwansei Gakum University |
| 3rd Author's Name | SHIMPEI Tamura |
| 3rd Author's Affiliation | Kwansei Gakum University |
| 4th Author's Name | Hiroyuki TOMIYAMA |
| 4th Author's Affiliation | Ritsumeikan University |
| 5th Author's Name | Hiroyuki KANBARA |
| 5th Author's Affiliation | ASTEM RI/KYOTO |
| Date | 2013-01-16 |
| Paper # | VLD2012-119,CPSY2012-68,RECONF2012-73 |
| Volume (vol) | vol.112 |
| Number (no) | 377 |
| Page | pp.pp.- |
| #Pages | 5 |
| Date of Issue | |