Presentation 2013-01-16
Design and Performance Evaluation of RSA Encryption Processor Using Signed-Digit Number Arithmetic
Junichi ASAOKA, Yuki TANAKA, Shugang WEI,
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Abstract(in English) RSA encryption processing spends a lot of time on modular exponentiation of long word length, therefore the speed of the encryption is an important problem. By introducing a signed-digit (SD) number arithmetic, residue arithmetic without carry propagation can be performed. In this paper, we propose modulo m multiplication circuits using signed-digit number arithmetic. By performance evaluation of RSA encryption circuit using the proposed multiplication circuits, the RSA encryption processor has high performance in comparison with encryption processor based on binary arithmetic.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Signed-Digit(SD) number / residue number system / SD modulo addition / SD modulo multiplication / RSA encryption
Paper # VLD2012-115,CPSY2012-64,RECONF2012-69
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Committee RECONF
Conference Date 2013/1/9(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Design and Performance Evaluation of RSA Encryption Processor Using Signed-Digit Number Arithmetic
Sub Title (in English)
Keyword(1) Signed-Digit(SD) number
Keyword(2) residue number system
Keyword(3) SD modulo addition
Keyword(4) SD modulo multiplication
Keyword(5) RSA encryption
1st Author's Name Junichi ASAOKA
1st Author's Affiliation Department of Production Science and Technology, Graduate School of Engineering, Gunma University()
2nd Author's Name Yuki TANAKA
2nd Author's Affiliation Department of Production Science and Technology, Graduate School of Engineering, Gunma University
3rd Author's Name Shugang WEI
3rd Author's Affiliation Department of Production Science and Technology, Graduate School of Engineering, Gunma University
Date 2013-01-16
Paper # VLD2012-115,CPSY2012-64,RECONF2012-69
Volume (vol) vol.112
Number (no) 377
Page pp.pp.-
#Pages 6
Date of Issue