| Presentation | 2013-01-16 An Architecture for IPv6 Lookup Using Parallel Index Generation Units Hiroki NAKAHARA, Tsutomu SASAO, Munehiro MATSUURA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper shows an area-efficiency and high-performance architecture for the IPv6 lookup using parallel index generation units (IGUs) and a priority encoder. To reduce the size of memory for the IGU, we adopt a liner transform and a row-shift decomposition. Also, this paper shows a design method for parallel IGUs with given prefixes. Experimental shows that, as for the normalized area and lookup speed, our architecture outperforms existing FPGA realizations. |
| Keyword(in Japanese) | (See Japanese page) |
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| Paper # | VLD2012-111,CPSY2012-60,RECONF2012-65 |
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| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2013/1/9(1days) |
| Place (in Japanese) | (See Japanese page) |
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| Topics (in Japanese) | (See Japanese page) |
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| Registration To | Reconfigurable Systems (RECONF) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An Architecture for IPv6 Lookup Using Parallel Index Generation Units |
| Sub Title (in English) | |
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| 1st Author's Name | Hiroki NAKAHARA |
| 1st Author's Affiliation | Faculty of Engineering, Kagoshima University() |
| 2nd Author's Name | Tsutomu SASAO |
| 2nd Author's Affiliation | Department of Creative Informatics, Kyushu Institute of Technology |
| 3rd Author's Name | Munehiro MATSUURA |
| 3rd Author's Affiliation | Department of Creative Informatics, Kyushu Institute of Technology |
| Date | 2013-01-16 |
| Paper # | VLD2012-111,CPSY2012-60,RECONF2012-65 |
| Volume (vol) | vol.112 |
| Number (no) | 377 |
| Page | pp.pp.- |
| #Pages | 6 |
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