Presentation	2013-01-16 A Design Method of Network-on-Chip Architecture for FPGA Hideki KATABAMI, Hiroshi SAITO,
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Abstract(in English)	This paper proposes a design method for a Globally-Asynchronous Locally-Synchronous Net-work-on-Chip (GALS-NoC) on Altera field programmable gate array (FPGA). In GALS-NoC, each NoC node such as a processor can be operated with independent clock signal. The communication is performed asynchronously without using a global clock signal. Hence, GALS-NoC is potentially high performance and low power In the experiments, this paper evaluates the area, performance, power consumption, and energy consumption of the designed GALS-NoC comparing with a single clock NoC and a multi clock NoC.
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Keyword(in English)	Network-on-Chip / FPGA / GALS-NoC
Paper #	VLD2012-108,CPSY2012-57,RECONF2012-62
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Conference Information
Committee	RECONF
Conference Date	2013/1/9(1days)
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Paper Information
Registration To	Reconfigurable Systems (RECONF)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	A Design Method of Network-on-Chip Architecture for FPGA
Sub Title (in English)
Keyword(1)	Network-on-Chip
Keyword(2)	FPGA
Keyword(3)	GALS-NoC
1st Author's Name	Hideki KATABAMI
1st Author's Affiliation	Graduate School of Computer Science and Engineering, the University of Aizu()
2nd Author's Name	Hiroshi SAITO
2nd Author's Affiliation	Graduate School of Computer Science and Engineering, the University of Aizu
Date	2013-01-16
Paper #	VLD2012-108,CPSY2012-57,RECONF2012-62
Volume (vol)	vol.112
Number (no)	377
Page	pp.pp.-
#Pages	6
Date of Issue