| Presentation | 2013-01-16 Architecture Evaluation of a Reconfigurable Device MPLD Tomoya YAMASHITA, Masato INAGI, Kazuya TANIGAWA, Tetsuo HIRONAKA, Takashi ISHIGURO, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this paper, we discuss the detailed structure of MPLD, an architecture for realizing reconfigurable devices MPLD consists of small memories connected by pairs of address and data lines (AD pairs) These memories, called MLUTs, are used as LUTs to realize logic cells, and also switch blocks to realize wires between the logic cells Thus, the number of AD pairs per MLUT and the connection pattern among MLUTs by AD pairs greatly affect the performance and acceptable size of circuits mapped to the MPLD Therefore, we compare a variety of MPLD architectures, which have the different numbers of AD pairs per MLUT and the different connection patterns among MLUTs, in some metrics |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | MPLD / PLD / FPGA / architecture / Place-and-Route |
| Paper # | VLD2012-107,CPSY2012-56,RECONF2012-61 |
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| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2013/1/9(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Vice Chair | |
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| Paper Information | |
| Registration To | Reconfigurable Systems (RECONF) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Architecture Evaluation of a Reconfigurable Device MPLD |
| Sub Title (in English) | |
| Keyword(1) | MPLD |
| Keyword(2) | PLD |
| Keyword(3) | FPGA |
| Keyword(4) | architecture |
| Keyword(5) | Place-and-Route |
| 1st Author's Name | Tomoya YAMASHITA |
| 1st Author's Affiliation | Graduate School of Information Sciences, Hiroshima City University() |
| 2nd Author's Name | Masato INAGI |
| 2nd Author's Affiliation | Graduate School of Information Sciences, Hiroshima City University |
| 3rd Author's Name | Kazuya TANIGAWA |
| 3rd Author's Affiliation | Graduate School of Information Sciences, Hiroshima City University |
| 4th Author's Name | Tetsuo HIRONAKA |
| 4th Author's Affiliation | Graduate School of Information Sciences, Hiroshima City University |
| 5th Author's Name | Takashi ISHIGURO |
| 5th Author's Affiliation | Taiyo Yuden Co Ltd |
| Date | 2013-01-16 |
| Paper # | VLD2012-107,CPSY2012-56,RECONF2012-61 |
| Volume (vol) | vol.112 |
| Number (no) | 377 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |