| Presentation | 2013/1/10 Effects of Deep Trapping States at High Temperatures on Transient Performances of A1GaN/GaN HFETs KENICHIRO TANAKA, Masahiro ISHIDA, Tetsuzo UEDA, Tsuyoshi TANAKA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Kinetic studies on the current collapse of a normally-off AlGaN/GaN heterostructure field effect tran-sistor under a high voltage have been performed above room temperature The on-state resistance after the on switching from the off state increases at high temperatures, contrary to the expectation that the emission of elec-trons is enhanced at elevated temperatures This result indicates that elevating the temperature enhances not only the emission of electrons but also their capture We experimentally observe that the enhancement of the capture process at high temperatures originates from the energy barrier for the capture of electrons, the value of which is determined to be 0.17 ± 0.04 eV The origin of the energy barrier for the capture process is explained by a configuration coordinate diagram. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | current collapse / GaN / A1GaN / HFET / HEMT / configuration coordinate diagram |
| Paper # | ED2012-124 |
| Date of Issue |
| Conference Information | |
| Committee | ED |
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| Conference Date | 2013/1/10(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Electron Devices (ED) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Effects of Deep Trapping States at High Temperatures on Transient Performances of A1GaN/GaN HFETs |
| Sub Title (in English) | |
| Keyword(1) | current collapse |
| Keyword(2) | GaN |
| Keyword(3) | A1GaN |
| Keyword(4) | HFET |
| Keyword(5) | HEMT |
| Keyword(6) | configuration coordinate diagram |
| 1st Author's Name | KENICHIRO TANAKA |
| 1st Author's Affiliation | Semiconductor Devices Development Center, Industrial Devices Company, Panasonic Corporation() |
| 2nd Author's Name | Masahiro ISHIDA |
| 2nd Author's Affiliation | Semiconductor Devices Development Center, Industrial Devices Company, Panasonic Corporation |
| 3rd Author's Name | Tetsuzo UEDA |
| 3rd Author's Affiliation | Semiconductor Devices Development Center, Industrial Devices Company, Panasonic Corporation |
| 4th Author's Name | Tsuyoshi TANAKA |
| 4th Author's Affiliation | Semiconductor Devices Development Center, Industrial Devices Company, Panasonic Corporation |
| Date | 2013/1/10 |
| Paper # | ED2012-124 |
| Volume (vol) | vol.112 |
| Number (no) | 380 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |