Presentation | 2013-01-17 Low latency network topology using multiple links at each host Ryuta KAWANO, Ikki FUJIWARA, Hiroki MATSUTANI, Hideharu AMANO, Michihiro KOIBUCHI, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | End-to-end network latency has become an important issue for parallel application on large-scale High Performance Computing (HPC) systems. It is thus necessary to build HPC systems as high-degree topologies by using high-radix switches. We have recently proposed a method to build topologies with such switches by adding random switch-to-switch links on a base regular topology. In this report, we extend the method by adding multiple links between a single host and multiple switches. Results obtained with flit-level discrete event simulation show that our random host-link topologies achieved comparable throughput with latency up to 49% lower than that of baseline topologies with link aggregation. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Topology / interconnection networks / high performance computing / high-radix switches |
Paper # | VLD2012-128,CPSY2012-77,RECONF2012-82 |
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Conference Information | |
Committee | VLD |
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Conference Date | 2013/1/9(1days) |
Place (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | VLSI Design Technologies (VLD) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Low latency network topology using multiple links at each host |
Sub Title (in English) | |
Keyword(1) | Topology |
Keyword(2) | interconnection networks |
Keyword(3) | high performance computing |
Keyword(4) | high-radix switches |
1st Author's Name | Ryuta KAWANO |
1st Author's Affiliation | Keio University() |
2nd Author's Name | Ikki FUJIWARA |
2nd Author's Affiliation | National Institute of Informatics:JST |
3rd Author's Name | Hiroki MATSUTANI |
3rd Author's Affiliation | Keio University |
4th Author's Name | Hideharu AMANO |
4th Author's Affiliation | Keio University |
5th Author's Name | Michihiro KOIBUCHI |
5th Author's Affiliation | National Institute of Informatics:JST |
Date | 2013-01-17 |
Paper # | VLD2012-128,CPSY2012-77,RECONF2012-82 |
Volume (vol) | vol.112 |
Number (no) | 375 |
Page | pp.pp.- |
#Pages | 6 |
Date of Issue |