Presentation | 2013-03-14 Development of High speed Network Intrusion Detection System with High Scalability Using High-performance FPGA Mamoru SEKIYAMA, Kenji TODA, Tetsuo KOTOKU, |
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PDF Download Page | PDF download Page Link |
Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | We developed intrusion detection system (IDS), that uses pattern matching circuit for Snort rules, on a high-performance FPGA testbed board with six 10GbE ports. The developed system can process intrusion detection on three 10GbE data streams individually. We also realized real-time IDS processing on three 10GbE data streams. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | FPGA / Intrusion Detection / 10G bit Ethernet / Snort |
Paper # | CPSY2012-96,DC2012-102 |
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Conference Information | |
Committee | CPSY |
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Conference Date | 2013/3/6(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | Computer Systems (CPSY) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Development of High speed Network Intrusion Detection System with High Scalability Using High-performance FPGA |
Sub Title (in English) | |
Keyword(1) | FPGA |
Keyword(2) | Intrusion Detection |
Keyword(3) | 10G bit Ethernet |
Keyword(4) | Snort |
1st Author's Name | Mamoru SEKIYAMA |
1st Author's Affiliation | National Institute of Advanced Industrial Science and Technology (AIST)() |
2nd Author's Name | Kenji TODA |
2nd Author's Affiliation | National Institute of Advanced Industrial Science and Technology (AIST) |
3rd Author's Name | Tetsuo KOTOKU |
3rd Author's Affiliation | National Institute of Advanced Industrial Science and Technology (AIST) |
Date | 2013-03-14 |
Paper # | CPSY2012-96,DC2012-102 |
Volume (vol) | vol.112 |
Number (no) | 481 |
Page | pp.pp.- |
#Pages | 5 |
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