Presentation 2013/3/6
Investigation and Improvement Techniques on the Impact of TLB misses in Real-Time Systems
KATO TOSHIKAZU, ISHIKAWA TAKUYA, HONDA SHINYA, TAKADA HIROAKI,
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Abstract(in English) In recent years, memory protection for real-time systems is needed to ensure safety of the systerns. The MMU used for memory protection uses the TLB which is a caching mechanism. When using the TLB in real-time systems, the worst-case execution time (WCET)is estimated pessimistically, because it is difficult to predict the occurrence of the TLB misses. In this paper, first, we evaluate the impact of TLB misses on the WCET. Secondly, we propose methods to control the occurrence of TLB misses by using the TLB locking mechanism. The result of evaluation shows the effectiveness of the proposed methods.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Real-time system / TLB miss / Worst-case execution time / TLB locking
Paper # Vol.2013-SLDM-160 No.27,Vol.2013-EMB-28 No.27
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Committee CPSY
Conference Date 2013/3/6(1days)
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Paper Information
Registration To Computer Systems (CPSY)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Investigation and Improvement Techniques on the Impact of TLB misses in Real-Time Systems
Sub Title (in English)
Keyword(1) Real-time system
Keyword(2) TLB miss
Keyword(3) Worst-case execution time
Keyword(4) TLB locking
1st Author's Name KATO TOSHIKAZU
1st Author's Affiliation Graduate School of Information Science, Nagoya University()
2nd Author's Name ISHIKAWA TAKUYA
2nd Author's Affiliation Graduate School of Information Science, Nagoya University
3rd Author's Name HONDA SHINYA
3rd Author's Affiliation Graduate School of Information Science, Nagoya University
4th Author's Name TAKADA HIROAKI
4th Author's Affiliation Graduate School of Information Science, Nagoya University
Date 2013/3/6
Paper # Vol.2013-SLDM-160 No.27,Vol.2013-EMB-28 No.27
Volume (vol) vol.112
Number (no) 481
Page pp.pp.-
#Pages 6
Date of Issue