| Presentation | 2013-03-14 Asynchnorous Memory Machine Models with Barrier Synchronization Koji NAKANO, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The Discrete Memory Machine (DMM) and the Unified Memory Machine (UMM) are theoretical parallel computing models that capture the essence of the shared memory and the global memory of GPUs. It was assumed that warps (i.e. groups of threads)on the DMM and the UMM work synchronously in the round-robin manner. However, warps work asynchronously in the actual GPUs, in the sense that warps may be randomly (or arbitrarily」dispatched for execution. The first contribution of this paper is to introduce an asynchronous version of the DMM and the UMM, in which warps are arbitrarily dispatched. Instead, we assume that threads can execute the "syncthreads" instruction for barrier synchronization. Since the barrier synchronization operation is costly, we should evaluate and minimize the number of barrier synchronization operations performed by parallel algorithms. The second contribution of this paper is to show a parallel algorithm to compute the sum of n numbers in optimal computing time and few barrier synchronization steps. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | parallel computing models / parallel algorithms / asynchronous models / GPU / CUDA |
| Paper # | CPSY2012-93,DC2012-99 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2013/3/6(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Asynchnorous Memory Machine Models with Barrier Synchronization |
| Sub Title (in English) | |
| Keyword(1) | parallel computing models |
| Keyword(2) | parallel algorithms |
| Keyword(3) | asynchronous models |
| Keyword(4) | GPU |
| Keyword(5) | CUDA |
| 1st Author's Name | Koji NAKANO |
| 1st Author's Affiliation | School of Engineering, Hiroshima University() |
| Date | 2013-03-14 |
| Paper # | CPSY2012-93,DC2012-99 |
| Volume (vol) | vol.112 |
| Number (no) | 482 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |