Presentation 2013/3/6
A Trial for Reliability Hot spot Visualization for Large-scale Integrated Circuits
KATSUYA KINOSHITA, TOMOHIKO SUMI, TAMOTSU ISHIHARA, LIE LIN, MASAHIRO FUKUI,
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Abstract(in English) In recent large-scale integrated circuit, hot spot for reliability becomes a complicated function. This paper has visualized the risks by noise of power gating, rising time, power consumption, timing, etc. The visualization system is built by Windows PC and the dangerous place is high-lighted by the multi-layered visualization system. This display system has high flexibility. We have checked that it can be used as a base of future "visualization" system.
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Paper # Vol.2013-SLDM-160 No.18,Vol.2013-EMB-28 No.18
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Conference Date 2013/3/6(1days)
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Language JPN
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Title (in English) A Trial for Reliability Hot spot Visualization for Large-scale Integrated Circuits
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Keyword(1)
1st Author's Name KATSUYA KINOSHITA
1st Author's Affiliation Ritsumeikan University()
2nd Author's Name TOMOHIKO SUMI
2nd Author's Affiliation Graduate School of Ritsumeikan University
3rd Author's Name TAMOTSU ISHIHARA
3rd Author's Affiliation Graduate School of Ritsumeikan University
4th Author's Name LIE LIN
4th Author's Affiliation Graduate School of Ritsumeikan University
5th Author's Name MASAHIRO FUKUI
5th Author's Affiliation Graduate School of Ritsumeikan University
Date 2013/3/6
Paper # Vol.2013-SLDM-160 No.18,Vol.2013-EMB-28 No.18
Volume (vol) vol.112
Number (no) 482
Page pp.pp.-
#Pages 6
Date of Issue