Presentation	2013/3/6 Fast Performance Estimation Method for Variable Latency Circuits with Error Detection/Correction Mechanism ,
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Abstract(in English)	Variable Latency Circuits with Error Detection/Correction (VLEDC) have potential to improve the circuit performance. For designing high performance circuits in VLEDC, it is needed to estimate the circuit performance rapidly. So the analysis of dynamic delay distribution of VLEDC is essential. In this paper, we proposed a method to estimate the dynamic delay distribution and the circuit performance in VLEDC rapidly. We confirm that the estimation of circuit performance by our proposed method is close to the circuit performance observed in FPGA implementation.
Keyword(in Japanese)	(See Japanese page)
Keyword(in English)	Dynamic delay distribution / Error detection/correction / Variable latency circuits / Signal transition event
Paper #	Vol.2013-SLDM-160 No.16,Vol.2013-EMB-28 No.16
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Conference Information
Committee	DC
Conference Date	2013/3/6(1days)
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Paper Information
Registration To	Dependable Computing (DC)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	Fast Performance Estimation Method for Variable Latency Circuits with Error Detection/Correction Mechanism
Sub Title (in English)
Keyword(1)	Dynamic delay distribution
Keyword(2)	Error detection/correction
Keyword(3)	Variable latency circuits
Keyword(4)	Signal transition event
1st Author's Name
1st Author's Affiliation	Division of Electrical, Electronic and Information Engineering, Osaka University()
Date	2013/3/6
Paper #	Vol.2013-SLDM-160 No.16,Vol.2013-EMB-28 No.16
Volume (vol)	vol.112
Number (no)	482
Page	pp.pp.-
#Pages	6
Date of Issue