| Presentation | 2013-03-05 A Parallel Global Routing Method Sharing Routing Regions for Multi-Core Processors Yasuhiro SHINTANI, Masato INAGI, Shinobu NAGAYAMA, Shin'ichi WAKABAYASHI, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Parallel routing methods using various parallel computing environments have been proposed in existing studies for reducing routing design time in LSI design process. In this study, we choose a multi-core processor from these computing environments, and propose a multi-threaded parallel routing algorithm. In the proposed method, first, threads are created and the nets of the target netlist are equally distributed to the threads. Sharing the routing regions, each of the threads searches a candidate path of a net in parallel without synchronization. Then, each thread exclusively writes a candidate path to the routing regions as a determined path. Although the exclusive control is necessary when updating the routing regions, this asynchronous parallel routing reduces the wait time of the threads. If a candidate path of a net does not satisfy the constraints due to the asynchronous parallel routing, the net is re-routed. In experiments, we confirmed that our proposed method running on an 8-core processor was 7.1 times as fast as the sequential execution. In addition, we also confirmed that the routing quality was not degraded compared to the sequential execution. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | LSI / Routing design / Multi-core processors / Multi-thread |
| Paper # | VLD2012-150 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2013/2/25(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Parallel Global Routing Method Sharing Routing Regions for Multi-Core Processors |
| Sub Title (in English) | |
| Keyword(1) | LSI |
| Keyword(2) | Routing design |
| Keyword(3) | Multi-core processors |
| Keyword(4) | Multi-thread |
| 1st Author's Name | Yasuhiro SHINTANI |
| 1st Author's Affiliation | Graduate School of Information Sciences, Hiroshima City University() |
| 2nd Author's Name | Masato INAGI |
| 2nd Author's Affiliation | Graduate School of Information Sciences, Hiroshima City University |
| 3rd Author's Name | Shinobu NAGAYAMA |
| 3rd Author's Affiliation | Graduate School of Information Sciences, Hiroshima City University |
| 4th Author's Name | Shin'ichi WAKABAYASHI |
| 4th Author's Affiliation | Graduate School of Information Sciences, Hiroshima City University |
| Date | 2013-03-05 |
| Paper # | VLD2012-150 |
| Volume (vol) | vol.112 |
| Number (no) | 451 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |