Presentation 2013-03-04
APR-based Legalization Method
Shota HIRAE, Maho ISHIKAWA, Yasuhiro TAKASHIMA,
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Abstract(in English) In this paper, we propose a fast algorithm to solve the linear placement problem that is important for standard cell. In recent years, a progress of the LSI process achieves the increase of the elements on one chip. As a result, the large turn-around time of LSI becomes a main issue. To shorten the time, three-step placement, which consists of global placement, legalization, and detailed placement, is widely used. We focus on the process from legalization to detailed placement. We propose a fast legalization method that outputs the minimum total wirelength placement which satisfies the constraint to maintain the topology relation without overlap between cells. We confirm the efficiency of the proposed method empirically.
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Keyword(in English) APR / Linear placement / Wirelength Minimization / Legalization / single-row
Paper # VLD2012-139
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Committee VLD
Conference Date 2013/2/25(1days)
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Registration To VLSI Design Technologies (VLD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) APR-based Legalization Method
Sub Title (in English)
Keyword(1) APR
Keyword(2) Linear placement
Keyword(3) Wirelength Minimization
Keyword(4) Legalization
Keyword(5) single-row
1st Author's Name Shota HIRAE
1st Author's Affiliation Faculty of Environmental Engineering, The University of Kitakyushu()
2nd Author's Name Maho ISHIKAWA
2nd Author's Affiliation Faculty of Environmental Engineering, The University of Kitakyushu
3rd Author's Name Yasuhiro TAKASHIMA
3rd Author's Affiliation Faculty of Environmental Engineering, The University of Kitakyushu
Date 2013-03-04
Paper # VLD2012-139
Volume (vol) vol.112
Number (no) 451
Page pp.pp.-
#Pages 6
Date of Issue