| 講演名 | 2012-09-19 A Design Framework for Reconfigurable IPs with VLSI CADs , |
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| PDFダウンロードページ |  PDFダウンロードページへ |
| 抄録(和) | The conventional FPGA design CAD flows evaluate FPGA architecture by implementing benchmarks through the following steps:synthesis, technology mapping, clustering and placement and routing (P&R). The area and timing performance reports are derived from the P&R tool. The accuracy of the result is low but proved enough to evaluate architectures fairly. However, for a complete FPGA IP design, the architecture should be evaluated with standard cells by the full back-end design flow. We proposed a new FPGA routing tool, namely EasyRouter. By using simple HDL templates, the EasyRouter can automatically generate entire chip HDL codes and the configuration bitstream according to architecture definition and routing result. With these files, the FPGA IP can be evaluated with commercial VLSI CADs in high accuracy and reliability. |
| 抄録(英) | The conventional FPGA design CAD flows evaluate FPGA architecture by implementing benchmarks through the following steps:synthesis, technology mapping, clustering and placement and routing (P&R). The area and timing performance reports are derived from the P&R tool. The accuracy of the result is low but proved enough to evaluate architectures fairly. However, for a complete FPGA IP design, the architecture should be evaluated with standard cells by the full back-end design flow. We proposed a new FPGA routing tool, namely EasyRouter. By using simple HDL templates, the EasyRouter can automatically generate entire chip HDL codes and the configuration bitstream according to architecture definition and routing result. With these files, the FPGA IP can be evaluated with commercial VLSI CADs in high accuracy and reliability. |
| キーワード(和) | FPGA / CAD / Routing |
| キーワード(英) | FPGA / CAD / Routing |
| 資料番号 | RECONF2012-41 |
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| 研究会 | RECONF |
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| 開催期間 | 2012/9/11(から1日開催) |
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| 申込み研究会 | Reconfigurable Systems (RECONF) |
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| 本文の言語 | ENG |
| タイトル（和） | A Design Framework for Reconfigurable IPs with VLSI CADs |
| サブタイトル（和） | |
| タイトル（英） | A Design Framework for Reconfigurable IPs with VLSI CADs |
| サブタイトル（和） | |
| キーワード(1)（和/英） | FPGA / FPGA |
| キーワード(2)（和/英） | CAD / CAD |
| キーワード(3)（和/英） | Routing / Routing |
| 第 1 著者 氏名（和/英） | / Qian ZHAO |
| 第 1 著者 所属（和/英） | Graduate School of Science and Technology Kumamoto University Graduate School of Science and Technology Kumamoto University |
| 発表年月日 | 2012-09-19 |
| 資料番号 | RECONF2012-41 |
| 巻番号（vol） | vol.112 |
| 号番号（no） | 203 |
| ページ範囲 | pp.- |
| ページ数 | 6 |
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