Presentation | 2012-12-14 A Study of FPGA implementation of TV Filter Ryoutarou Narusawa, Syo Miura, Hiroyuki Tsuji, Tomoaki Kimura, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | The Total Variation (TV) filter, a the nonlinear filter that requires iterative process, achieves an excellent performance in the restoration of images degraded by Gaussian noise. In this report, we propose a hardware implementation of TV filter using FPGA, and examine our hardware design of TV filter. We implemented this hardware to Arria-II GX FPGA, and as a result, the logical block's usage rate was 30%, and the multiplier block's usage rate was 47%. Furthermore, we verified operation of this hardware, and it turns out that the error with software process was less than 5%. In future work, we will implement hardware including memory management and the iteration process of TV Filter. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | TV Filter / FPGA / Hardware Implementation |
Paper # | SIS2012-42 |
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Committee | SIS |
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Conference Date | 2012/12/6(1days) |
Place (in Japanese) | (See Japanese page) |
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Registration To | Smart Info-Media Systems (SIS) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | A Study of FPGA implementation of TV Filter |
Sub Title (in English) | |
Keyword(1) | TV Filter |
Keyword(2) | FPGA |
Keyword(3) | Hardware Implementation |
1st Author's Name | Ryoutarou Narusawa |
1st Author's Affiliation | Kanagawa Institute of Technology() |
2nd Author's Name | Syo Miura |
2nd Author's Affiliation | Kanagawa Institute of Technology |
3rd Author's Name | Hiroyuki Tsuji |
3rd Author's Affiliation | Kanagawa Institute of Technology |
4th Author's Name | Tomoaki Kimura |
4th Author's Affiliation | Kanagawa Institute of Technology |
Date | 2012-12-14 |
Paper # | SIS2012-42 |
Volume (vol) | vol.112 |
Number (no) | 348 |
Page | pp.pp.- |
#Pages | 6 |
Date of Issue |