Presentation	2012-09-21 Fault Analysis Based on Key Presumption for Multiple Errors Midori Ono, Masaya Yoshikawa,
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Abstract(in English)	Recently, handheld devices like smart-cards are used widely. These devices usually protect confidential information using security circuit with standard encryption. However, it was reported that fault analysis attack could retrieve the information from them. In its attack, an attacker produces some faults in the security circuit, and analyzes the faults output to retrieve information. Clock glitch is one of them and easily induces faults. But its output is difficult to analyze, because the faults occur in many positions of the circuit. We propose a new fault analysis method which utilizes fault's characteristic. In addition, we construct the fault attack environment in FPGA, and simulate fault attack. Simulation results proved the validity of the proposed method.
Keyword(in Japanese)	(See Japanese page)
Keyword(in English)	AES / Fault Analysis Attack / DFA
Paper #	ISEC2012-55
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Conference Information
Committee	ISEC
Conference Date	2012/9/14(1days)
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Paper Information
Registration To	Information Security (ISEC)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	Fault Analysis Based on Key Presumption for Multiple Errors
Sub Title (in English)
Keyword(1)	AES
Keyword(2)	Fault Analysis Attack
Keyword(3)	DFA
1st Author's Name	Midori Ono
1st Author's Affiliation	Department of Information Engineering Meijo University()
2nd Author's Name	Masaya Yoshikawa
2nd Author's Affiliation	Department of Information Engineering Meijo University
Date	2012-09-21
Paper #	ISEC2012-55
Volume (vol)	vol.112
Number (no)	211
Page	pp.pp.-
#Pages	7
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