| 講演名 | 2012-09-20 A High-Performance Multiplierless Hardware Architecture of the Transform Applied to H.265/HEVC Emerging Video Coding Standard , |
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| PDFダウンロードページ |  PDFダウンロードページへ |
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| 抄録(英) | This paper presents a hardware architecture of the transform applied in the emerging video coding standard-HEVC (High Efficiency Video Coding). The transform coding tool is one of the innovational feature adopted by HEVC, because of the variable transform matrix size (from 4x4 to 32x32), while the traditional transform size is 4x4 and 8x8 used by the H.264/AVC. The hardware design proposed in this paper focuses on low cost and high throughput. To obtain such objectives, some simplification strategies were adopted during the implementation, such as reusing part of larger size transform structure by smaller size, and turning multiplications by constant into shift and sum operations. Moreover, the transform architecture proposed in this paper was implemented in the form of pipeline structure. The designed architecture was described using Verilog HDL, and synthesis on an Altera Cyclone IV E FPGA. The results showed that the design achieved a maximum operation frequency of 114.29 MHz, and can process 190.50Msamples/s on average, allowing it to process Class A video sequences (2560x1600 pixels, 30fps) and Full HD sequences (1920x1080 pixels, 60fps). Therefore, the proposed architecture is capable to processing video sequences with high definition in real time. To the best of our knowledge, this is the first work in the literature that presents fully hardware results on FPGA platform for the HEVC transforms with a variable size from 4x4 to 32x32. |
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| キーワード(英) | HEVC / Transform / Hardware architecture / Pipeline structure |
| 資料番号 | SIS2012-18 |
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| 研究会 | SIS |
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| 開催期間 | 2012/9/13(から1日開催) |
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| 申込み研究会 | Smart Info-Media Systems (SIS) |
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| 本文の言語 | ENG |
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| タイトル（英） | A High-Performance Multiplierless Hardware Architecture of the Transform Applied to H.265/HEVC Emerging Video Coding Standard |
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| キーワード(1)（和/英） | / HEVC |
| 第 1 著者 氏名（和/英） | / Wenjun ZHAO |
| 第 1 著者 所属（和/英） | Dept. of Information Systems Engineering Graduate School of Information Science and Technology Osaka University Dept. of Information Systems Engineering Graduate School of Information Science and Technology Osaka University |
| 発表年月日 | 2012-09-20 |
| 資料番号 | SIS2012-18 |
| 巻番号（vol） | vol.112 |
| 号番号（no） | 207 |
| ページ範囲 | pp.- |
| ページ数 | 6 |
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