| Presentation | 2012-11-27 Network Performance of Multifunction On-chip Router Architectures Shinya TAKAMAEDA-YAMAZAKI, Naoki FUJIEDA, Kenji KISE, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In order to improve the chip-level dependability, we have proposed SmartCore system, NoC-based DMR (Dual Modular Redundant) mechanism by employing inherent redundancies of PEs in many-core processors. We also have proposed a multifunction on-chip router architecture that has additional capabilities to support DMR execution such as packet rendezvous and packet comparison. In this paper, in order to develop a sophisticated multifunction router with both low latency overhead of packet rendezvous in DMR execution and low hardware overhead, we compare the two on-chip router microarchitures with additional functions for DMR executions. The one is a minimal router microarchitecture with two additional buffers for packet comparison based on the standard on-chip router architecture. The other is an advanced router microarchitecture with an expanded crossbar for higher network performance. We implemented these two multifunction routers in Verilog HDL. We evaluated their network performance in DMR execution by using several common network traffic patterns. The evaluation result shows that the latency increase by DMR execution with the router with the expanded crossbar is 12.4% smaller than the increase of the minimal microarchitecture router in average. We also estimated their approximate area by using a standard FPGA design tool. The evaluation result shows that the area of the router with the advanced crossbar is about 62.9% larger than the area of the minimal microarchitecture router. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Network on Chip / Many-core Processor / Dual Modular Redundancy / Network Performance |
| Paper # | CPSY2012-52 |
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| Conference Information | |
| Committee | CPSY |
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| Conference Date | 2012/11/19(1days) |
| Place (in Japanese) | (See Japanese page) |
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| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Computer Systems (CPSY) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Network Performance of Multifunction On-chip Router Architectures |
| Sub Title (in English) | |
| Keyword(1) | Network on Chip |
| Keyword(2) | Many-core Processor |
| Keyword(3) | Dual Modular Redundancy |
| Keyword(4) | Network Performance |
| 1st Author's Name | Shinya TAKAMAEDA-YAMAZAKI |
| 1st Author's Affiliation | Graduate School of Information Science and Engineering Tokyo Institute of Technology:JSPS() |
| 2nd Author's Name | Naoki FUJIEDA |
| 2nd Author's Affiliation | Graduate School of Information Science and Engineering Tokyo Institute of Technology |
| 3rd Author's Name | Kenji KISE |
| 3rd Author's Affiliation | Graduate School of Information Science and Engineering Tokyo Institute of Technology |
| Date | 2012-11-27 |
| Paper # | CPSY2012-52 |
| Volume (vol) | vol.112 |
| Number (no) | 322 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |