Presentation 2012-11-28
A Scan-Out Power Reduction Method for Multi-Cycle BIST
Senling Wang, Yasuo Sato, Seiji Kajihara, Kohei Miyase,
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Abstract(in English) Excessive power dissipation in logic BIST is a serious problem. Although many low power BIST approaches that focus on scan-in power or capture power have been proposed, there are not so many techniques for scan-out power reduction due to the difficulty in controlling the captured test responses. In this paper, we propose a novel scan-out power reduction method for multi-cycle BIST that directly reduces scan-out power by modifying some flip-flops' values in scan chains at the last capture, and without sacrificing the test coverage.
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Keyword(in English) low power / BIST / multi-cycle test / shift power
Paper # VLD2012-102,DC2012-68
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Committee DC
Conference Date 2012/11/19(1days)
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Registration To Dependable Computing (DC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Scan-Out Power Reduction Method for Multi-Cycle BIST
Sub Title (in English)
Keyword(1) low power
Keyword(2) BIST
Keyword(3) multi-cycle test
Keyword(4) shift power
1st Author's Name Senling Wang
1st Author's Affiliation Kyushu Institute of Technology:Japan Science and Technology Agency, CREST()
2nd Author's Name Yasuo Sato
2nd Author's Affiliation Kyushu Institute of Technology:Japan Science and Technology Agency, CREST
3rd Author's Name Seiji Kajihara
3rd Author's Affiliation Kyushu Institute of Technology:Japan Science and Technology Agency, CREST
4th Author's Name Kohei Miyase
4th Author's Affiliation Kyushu Institute of Technology:Japan Science and Technology Agency, CREST
Date 2012-11-28
Paper # VLD2012-102,DC2012-68
Volume (vol) vol.112
Number (no) 321
Page pp.pp.-
#Pages 6
Date of Issue