Presentation	2012-11-28 A LSI-Package-Board co-evaluation of Power noise in the Digtal LSI Kumpei YOSHIKAWA, Yuta SASAKI, Kouji ICHIKAWA, Yoshiyuki SAITO, Makoto NAGATA,
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Abstract(in English)	Problems related with power noise in LSI system are getting prominent because of the higher integration and lower V_ voltage of an LSI chip. A Power noise simulation method that could use in various design phases is required for designing noise-tolerant and low-cost systems. The impedance profile of power delivery network (PDN) and circuit operations strongly affects the power noise characteristics. The simulation model that contains whole elements of system such as LSIs, packages, and boards is required. In this paper, we present the LSI-package-board combined power noise simulation model. Accuracy of the simulation model is confirmed by comparing the on-chip noise meaurement results using an on-chip noise monitor circuit and on-board noise measurement results using a magnetic probe method.
Keyword(in Japanese)	(See Japanese page)
Keyword(in English)	Power noise / Power integrity / EMC / Noise simulation
Paper #	VLD2012-91,DC2012-57
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Committee	DC
Conference Date	2012/11/19(1days)
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Paper Information
Registration To	Dependable Computing (DC)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	A LSI-Package-Board co-evaluation of Power noise in the Digtal LSI
Sub Title (in English)
Keyword(1)	Power noise
Keyword(2)	Power integrity
Keyword(3)	EMC
Keyword(4)	Noise simulation
1st Author's Name	Kumpei YOSHIKAWA
1st Author's Affiliation	Graduate School of System Informatics, Kobe University()
2nd Author's Name	Yuta SASAKI
2nd Author's Affiliation	Graduate School of System Informatics, Kobe University
3rd Author's Name	Kouji ICHIKAWA
3rd Author's Affiliation	DENSO CORPORATION
4th Author's Name	Yoshiyuki SAITO
4th Author's Affiliation	Panasonic corporation
5th Author's Name	Makoto NAGATA
5th Author's Affiliation	Graduate School of System Informatics, Kobe University:JST, CREST
Date	2012-11-28
Paper #	VLD2012-91,DC2012-57
Volume (vol)	vol.112
Number (no)	321
Page	pp.pp.-
#Pages	6
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