| Presentation | 2012-11-27 A Speculative Execution Method for Indefinite Loops in High Level Synthesis Tatuma ARAKI, Hideki TAKASE, Kazuyosi TAKAGI, Naohumi TAKAGI, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | It is important to ensure the parallelism of the synthesized circuits in high level synthesis, where digital designs are synthesized from their behavioral descriptions. In this report, we focus on indefinite loops whose number of iterations are decided during execution. Our proposed method executes processes in the loop and the process of loop count computation in parallel because processes in the loop can be pre-executed while loop count computation. The control-data-flow graph of the loop is converted to two processes, one for speculative execution, another for guaranteeing consistency of the speculative execution. Our method synthesizes additional hardware modules, a memory module, a module to read from and write to the memory, and a loop controller. loop count computation in parallel by additional hardware. We evaluated the effectiveness with an example program which has indefinite loops. The reduction of the number of cycle was conducted by applying the proposed method. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | High level synthesis / speculation / control-data-flow graph / parallelization |
| Paper # | VLD2012-76,DC2012-42 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2012/11/19(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Speculative Execution Method for Indefinite Loops in High Level Synthesis |
| Sub Title (in English) | |
| Keyword(1) | High level synthesis |
| Keyword(2) | speculation |
| Keyword(3) | control-data-flow graph |
| Keyword(4) | parallelization |
| 1st Author's Name | Tatuma ARAKI |
| 1st Author's Affiliation | Communications and Computer Engineering, Graduate School of Informatics, Kyoto University() |
| 2nd Author's Name | Hideki TAKASE |
| 2nd Author's Affiliation | Communications and Computer Engineering, Graduate School of Informatics, Kyoto University |
| 3rd Author's Name | Kazuyosi TAKAGI |
| 3rd Author's Affiliation | Communications and Computer Engineering, Graduate School of Informatics, Kyoto University |
| 4th Author's Name | Naohumi TAKAGI |
| 4th Author's Affiliation | Communications and Computer Engineering, Graduate School of Informatics, Kyoto University |
| Date | 2012-11-27 |
| Paper # | VLD2012-76,DC2012-42 |
| Volume (vol) | vol.112 |
| Number (no) | 321 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |