Presentation 2012-11-26
A Low-Power and Area-Efficient Radiation-Hard Redundant Flip-Flop : DICE ACFF
Kanto KUBOTA, Masuda MASAKI, Kazutoshi KOBAYASHI,
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Abstract(in English) Process scaling makes LSI less reliable to soft errors and increases power. We propose a low-power highly-reliable flop-flop called DICE ACFF implemented with the Dual-interlocked storage cell (DICE) and the Adaptive-coupled FF (ACFF). Its power is less than transmission-gate FFs if Data Activity less than 30%. The Dice structure in DICE ACFF has a capability to recover from a single-node upset. The DICE ACFF achieves highly-reliable operations with low power.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Power / Area-Efficient / Radiation-Hard Redundant Flip-Flop / Dual Interlocked storage Cell (DICE) / Adaptive-Coupling FF (ACFF)
Paper # VLD2012-71,DC2012-37
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Committee DC
Conference Date 2012/11/19(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Low-Power and Area-Efficient Radiation-Hard Redundant Flip-Flop : DICE ACFF
Sub Title (in English)
Keyword(1) Power
Keyword(2) Area-Efficient
Keyword(3) Radiation-Hard Redundant Flip-Flop
Keyword(4) Dual Interlocked storage Cell (DICE)
Keyword(5) Adaptive-Coupling FF (ACFF)
1st Author's Name Kanto KUBOTA
1st Author's Affiliation Kyoto Institute of Technology()
2nd Author's Name Masuda MASAKI
2nd Author's Affiliation Kyoto Institute of Technology
3rd Author's Name Kazutoshi KOBAYASHI
3rd Author's Affiliation Kyoto Institute of Technology:JST, CREST
Date 2012-11-26
Paper # VLD2012-71,DC2012-37
Volume (vol) vol.112
Number (no) 321
Page pp.pp.-
#Pages 6
Date of Issue