| Presentation | 2012-11-26 Impact of Body-Biasing Technique on RTN-induced Delay Fluctuation Takashi MATSUMOTO, Kazutoshi KOBAYASHI, Hidetoshi ONODERA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Designing reliable systems has become more difficult in recent years. In this paper, statistical nature of RTN-induced delay fluctuation is described by measuring 1,655 ROs fabricated in a commercial 40nm CMOS technology. We also investigated the impact of body-biasing technique on RTN-induced circuit delay fluctuation. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | dependable VLSI / CMOS / RTN / Body-Biasing Technique |
| Paper # | VLD2012-70,DC2012-36 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2012/11/19(1days) |
| Place (in Japanese) | (See Japanese page) |
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| Topics (in Japanese) | (See Japanese page) |
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| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Impact of Body-Biasing Technique on RTN-induced Delay Fluctuation |
| Sub Title (in English) | |
| Keyword(1) | dependable VLSI |
| Keyword(2) | CMOS |
| Keyword(3) | RTN |
| Keyword(4) | Body-Biasing Technique |
| 1st Author's Name | Takashi MATSUMOTO |
| 1st Author's Affiliation | Graduate School of Informatics, Kyoto University() |
| 2nd Author's Name | Kazutoshi KOBAYASHI |
| 2nd Author's Affiliation | Graduate School of Science and Technology, Kyoto Institute of Technology:JST CREST |
| 3rd Author's Name | Hidetoshi ONODERA |
| 3rd Author's Affiliation | Graduate School of Informatics, Kyoto University:JST CREST |
| Date | 2012-11-26 |
| Paper # | VLD2012-70,DC2012-36 |
| Volume (vol) | vol.112 |
| Number (no) | 321 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |