Presentation | 2012-11-26 A Delay Tuning Method of Programmable Delay Element with Two Delay Values for Yield Improvement Hayato MASHIKO, Yukihide KOHIRA, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | Due to progressing the process technology in LSI and increasing delay variations of interconnection and gate delays after fabrication, timing violations cause significant reduction in the yield of LSI chips. To recover the timing violations, programmable delay elements called PDEs are inserted into the clock tree before fabrication and their delays are tuned after fabrication. In this paper, we use PDEs with two delay value and propose a PDE structure, a design flow for circuits with the PDEs using commercial IC design tools, and a delay tuning method of the PDE for the yield improvement and the reduction of the number of tests. Experimental results show that the proposed method is effective. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Delay variation / timing violation / yield / programmable delay element |
Paper # | VLD2012-69,DC2012-35 |
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Committee | DC |
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Conference Date | 2012/11/19(1days) |
Place (in Japanese) | (See Japanese page) |
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Registration To | Dependable Computing (DC) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | A Delay Tuning Method of Programmable Delay Element with Two Delay Values for Yield Improvement |
Sub Title (in English) | |
Keyword(1) | Delay variation |
Keyword(2) | timing violation |
Keyword(3) | yield |
Keyword(4) | programmable delay element |
1st Author's Name | Hayato MASHIKO |
1st Author's Affiliation | School of Computer Science, the University of Aizu() |
2nd Author's Name | Yukihide KOHIRA |
2nd Author's Affiliation | School of Computer Science, the University of Aizu |
Date | 2012-11-26 |
Paper # | VLD2012-69,DC2012-35 |
Volume (vol) | vol.112 |
Number (no) | 321 |
Page | pp.pp.- |
#Pages | 6 |
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