Presentation	2012-11-26 High Field Reliability Using Built-in Self Test Seiji Kajihara,
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Abstract(in English)	On-line test based on delay measurement at power-on/off time or at system idle time of a system allows us to detect delay degradation of logic circuits and confirm their marginality. Such a test can predict a circuit failure caused by circuit aging. Therefore it is useful to avoid sudden system down, and we can make the system to be reliable. In this talk we discuss on the required features that differentiate field test from traditional manufacturing test, with respect to BIST (built-in self test) for high field reliability, and then introduce test technology DART that we recently developed in a JST CREST project.
Keyword(in Japanese)	(See Japanese page)
Keyword(in English)	Dependability / On-line test / Built-In self test / Fault tolerance
Paper #	VLD2012-65,DC2012-31
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Conference Information
Committee	DC
Conference Date	2012/11/19(1days)
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Paper Information
Registration To	Dependable Computing (DC)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	High Field Reliability Using Built-in Self Test
Sub Title (in English)
Keyword(1)	Dependability
Keyword(2)	On-line test
Keyword(3)	Built-In self test
Keyword(4)	Fault tolerance
1st Author's Name	Seiji Kajihara
1st Author's Affiliation	Kyushu Institute of Technology:Japan Science and Technology Agency, CREST()
Date	2012-11-26
Paper #	VLD2012-65,DC2012-31
Volume (vol)	vol.112
Number (no)	321
Page	pp.pp.-
#Pages	6
Date of Issue