| Presentation | 2012-11-26 A Temperature-Aware High-Level Synthesis Algorithm for Regular-Distributed-Register Architectures based on Accurate Energy Consumption Estimation Kazushi KAWAMURA, Masao YANAGISAWA, Nozomu TOGAWA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | With process technology scaling, heat problems in IC chips as well as increasing the average interconnection delays are becoming serious issues. Recently, we have proposed a binding and allocation algorithm for regular-distributed-register architectures (RDR architectures) with the objective of minimizing the peak temperature. In this paper, we propose an improved thermal-aware high-level synthesis algorithm for RDR architectures. The RDR architecture divides the entire chip into islands regularly. Firstly, our algorithm balances the energy consumption among islands through re-binding to functional units. Secondly, it accurately estimates the energy consumption in each island and minimizes the maximum energy consumption among islands through re-allocating new additional functional units. Experimental results demonstrate that our algorithm reduces the peak temperature by up to 15.42% compared with the conventional approaches. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | high-level synthesis / RDR architectures / temperature-aware / hot spots / interconnection delays |
| Paper # | VLD2012-61,DC2012-27 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2012/11/19(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Temperature-Aware High-Level Synthesis Algorithm for Regular-Distributed-Register Architectures based on Accurate Energy Consumption Estimation |
| Sub Title (in English) | |
| Keyword(1) | high-level synthesis |
| Keyword(2) | RDR architectures |
| Keyword(3) | temperature-aware |
| Keyword(4) | hot spots |
| Keyword(5) | interconnection delays |
| 1st Author's Name | Kazushi KAWAMURA |
| 1st Author's Affiliation | Grad. of Fundamental Science and Engineering, Waseda University() |
| 2nd Author's Name | Masao YANAGISAWA |
| 2nd Author's Affiliation | Grad. of Fundamental Science and Engineering, Waseda University |
| 3rd Author's Name | Nozomu TOGAWA |
| 3rd Author's Affiliation | Grad. of Fundamental Science and Engineering, Waseda University |
| Date | 2012-11-26 |
| Paper # | VLD2012-61,DC2012-27 |
| Volume (vol) | vol.112 |
| Number (no) | 321 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |