| Presentation | 2012-11-28 AES Cryptographic Circuit utilizing Dual-Rail RSL Memory Technique Yuuki HASHIMOTO, Mitsuru SHIOZAKI, Takaya KUBOTA, Takeshi FUJINO, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Tamper LSI design methodology has to be applied in order to implement secure cryptographic circuit, which is resistant to side-channel attacks such as PA (Power Analysis). We have proposed the PA-resistant countermeasure called the "dual-rail RSL memory". On the cryptographic circuit using this scheme, the dual-rail complementary approach is used to consume constant power regardless of input/output values. And, the masking technique is used to hide correlations between the secret key and the power consumptions. A prototype AES chip was designed and fabricated with a 0.18μmCMOS technology. The circuit area and the power consumption during one encryption operation are 900,191um^2 and 22.24nJ, respectively, and the proposed scheme achieves low area and low power compared with other countermeasures. In addition, the number of traces in order to disclose all secret byte keys is over 10^6, and the sufficient resistance against PA is demonstrated in the experimental results. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Side-Channel Attack / AES / DPA / CPA / Dual-Rail RSL Memory |
| Paper # | CPM2012-120,ICD2012-84 |
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| Conference Information | |
| Committee | CPM |
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| Conference Date | 2012/11/20(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Component Parts and Materials (CPM) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | AES Cryptographic Circuit utilizing Dual-Rail RSL Memory Technique |
| Sub Title (in English) | |
| Keyword(1) | Side-Channel Attack |
| Keyword(2) | AES |
| Keyword(3) | DPA |
| Keyword(4) | CPA |
| Keyword(5) | Dual-Rail RSL Memory |
| 1st Author's Name | Yuuki HASHIMOTO |
| 1st Author's Affiliation | Graduate School of Science and Technology, Ritsumeikan University() |
| 2nd Author's Name | Mitsuru SHIOZAKI |
| 2nd Author's Affiliation | Research Organization of Science and Engineering, Ritsumeikan University |
| 3rd Author's Name | Takaya KUBOTA |
| 3rd Author's Affiliation | Research Organization of Science and Engineering, Ritsumeikan University |
| 4th Author's Name | Takeshi FUJINO |
| 4th Author's Affiliation | Department of Science and Engineering, Ritsumeikan University |
| Date | 2012-11-28 |
| Paper # | CPM2012-120,ICD2012-84 |
| Volume (vol) | vol.112 |
| Number (no) | 323 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |