| Presentation | 2012-11-27 Overview of 3D Integration Technology and Challenges for Volume Production Kangwook LEE, Takafumi FUKUSHIMA, Tetsu TANAKA, Mitsumasa KOYANAGI, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Three-dimensional (3-D) integration is an emerging technology, which vertically stacks and interconnects multiple materials, technologies, and functional components such as processor, memory, sensors, logic, analog, and power ICs into one stacked chip to form highly integrated systems. Since CMOS device scaling has stalled, 3D integration technology allows extending Moore's law to ever high density, higher functionality, higher performance, and more diverse materials and devices to be integrated with lower cost. The potential benefits of 3D integration can vary depending on approach; increased multi-functionality, increased performance, increased data bandwidth, reduced power, small form factor, reduced packaging volume, increased yield and reliability, flexible heterogeneous integration. However, 3D integration technology has still many challenges for commercialization. In this paper, we describe an overview and future perspectives of the 3D integration technologies. The reliability issues of electrical and mechanical constraints induced by Cu TSV, micro-bumps, wafer thinning, and wafer bonding in the 3D thinned wafer are serious challenges for volume production. The paper focus on the local stress/strain effects induced by Cu TSV, micro-bump, and wafer thinning and the metal contamination effects induced by Cu TSV, and wafer thinning on the device reliabilities in the thinned wafer. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | 3D LSI / TSV(through silicon via) / Micro-bumping / Thermo-mechanical Stress / Cu contamination |
| Paper # | CPM2012-115,ICD2012-79 |
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| Conference Information | |
| Committee | CPM |
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| Conference Date | 2012/11/20(1days) |
| Place (in Japanese) | (See Japanese page) |
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| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Component Parts and Materials (CPM) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Overview of 3D Integration Technology and Challenges for Volume Production |
| Sub Title (in English) | |
| Keyword(1) | 3D LSI |
| Keyword(2) | TSV(through silicon via) |
| Keyword(3) | Micro-bumping |
| Keyword(4) | Thermo-mechanical Stress |
| Keyword(5) | Cu contamination |
| 1st Author's Name | Kangwook LEE |
| 1st Author's Affiliation | Dept. of Bioengineering and Robotics, Tohoku Univ.() |
| 2nd Author's Name | Takafumi FUKUSHIMA |
| 2nd Author's Affiliation | Dept. of Bioengineering and Robotics, Tohoku Univ. |
| 3rd Author's Name | Tetsu TANAKA |
| 3rd Author's Affiliation | Dept. of Biomedical Engineering, Tohoku Univ. |
| 4th Author's Name | Mitsumasa KOYANAGI |
| 4th Author's Affiliation | Dept. of Bioengineering and Robotics, Tohoku Univ. |
| Date | 2012-11-27 |
| Paper # | CPM2012-115,ICD2012-79 |
| Volume (vol) | vol.112 |
| Number (no) | 323 |
| Page | pp.pp.- |
| #Pages | 8 |
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