Presentation | 2012-11-26 Secure Scan Architecture Using State Dependent Scan Flip-Flop with Key-Based Configuration against Scan-Based Attack Yuta ATOBE, Youhua SHI, Masao YANAGISAWA, Nozomu TOGAWA, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | Secure cryptographic LSIs is intensively used in order to perform confidential operation. Scan test has become the most widely adopted test technique to ensure the correctness of manufactured LSIs, in which through the scan chains the internal states of the circuit under test (CUT) can be controlled and observed externally. However, scan chains using scan test might carry the risk of being misused for secret information leakage. Therefore a secure scan architecture using SDSFF (State Dependent Scan Flip-Flop) against scan-based attack which achieves high security without compromising the testability is proposed. In SDSFF, there is a problem which is the update timing of the latch which added to the scan FF. In this paper, we propose the update timing to online test without sacrificing the security. In our method, the latches are updated by result which the value of KEY which decided when designed compared with any FFs in a scan chain. We show that by using proposed method, neither the secret key nor the testability of vairous crypto circuits implementation is compromised, and the effectiveness of the proposed method. Experimental results on various crypto implementations show the effectiveness of the proposed method. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | scan chain / scan-based attack / secure scan architecture / crypto circuit / SDSFF |
Paper # | VLD2012-67,DC2012-33 |
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Committee | VLD |
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Conference Date | 2012/11/19(1days) |
Place (in Japanese) | (See Japanese page) |
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Registration To | VLSI Design Technologies (VLD) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Secure Scan Architecture Using State Dependent Scan Flip-Flop with Key-Based Configuration against Scan-Based Attack |
Sub Title (in English) | |
Keyword(1) | scan chain |
Keyword(2) | scan-based attack |
Keyword(3) | secure scan architecture |
Keyword(4) | crypto circuit |
Keyword(5) | SDSFF |
1st Author's Name | Yuta ATOBE |
1st Author's Affiliation | Grad. of Fundamental Science and Engineering, Waseda University() |
2nd Author's Name | Youhua SHI |
2nd Author's Affiliation | Waseda Institute for Advanced Study, Waseda University |
3rd Author's Name | Masao YANAGISAWA |
3rd Author's Affiliation | Grad. of Fundamental Science and Engineering, Waseda University |
4th Author's Name | Nozomu TOGAWA |
4th Author's Affiliation | Grad. of Fundamental Science and Engineering, Waseda University |
Date | 2012-11-26 |
Paper # | VLD2012-67,DC2012-33 |
Volume (vol) | vol.112 |
Number (no) | 320 |
Page | pp.pp.- |
#Pages | 6 |
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