Presentation 2012-11-26
Automated Identification of Performance Bottleneck on Embedded Systems for Architecture Exploration
Yuki ANDO, Seiya SHIBATA, Shinya HONDA, Hiroyuki TOMIYAMA, Hiroaki TAKADA,
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Abstract(in English) This paper presents a method to identify performance bottleneck on an embedded systems. At the same time, our method explores improvement rates on execution time and hardware area for performance bottleneck so that the system satisfies design constraints. Our method explores improvement rates with improved performance values which are estimated by changing the input information to the estimation tool. A case study on AES encryption and decryption application shows the advantages of our method.
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Keyword(in English) Bottleneck Analysis / Embedded Systems / Architecture Explorations
Paper # VLD2012-62,DC2012-28
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Conference Information
Committee VLD
Conference Date 2012/11/19(1days)
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Paper Information
Registration To VLSI Design Technologies (VLD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Automated Identification of Performance Bottleneck on Embedded Systems for Architecture Exploration
Sub Title (in English)
Keyword(1) Bottleneck Analysis
Keyword(2) Embedded Systems
Keyword(3) Architecture Explorations
1st Author's Name Yuki ANDO
1st Author's Affiliation Nagoya University:The Japan Society for the Promotion of Science()
2nd Author's Name Seiya SHIBATA
2nd Author's Affiliation Nagoya University
3rd Author's Name Shinya HONDA
3rd Author's Affiliation Nagoya University
4th Author's Name Hiroyuki TOMIYAMA
4th Author's Affiliation Ritsumeikan University
5th Author's Name Hiroaki TAKADA
5th Author's Affiliation Nagoya University
Date 2012-11-26
Paper # VLD2012-62,DC2012-28
Volume (vol) vol.112
Number (no) 320
Page pp.pp.-
#Pages 6
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