| Presentation | 2012-10-19 Secure Scan Architecture Using State Dependent Scan Flip-Flop with Key-Based Configuration on RSA Circuit Yuta ATOBE, Youhua SHI, Masao YANAGISAWA, Nozomu TOGAWA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Scan test is one of the useful design for testability techniques, which can detect circuit failure efficiently. However, it has been reported that it's possible to retrieve secret keys from cryptographic LSIs through scan chains. Therefore a secure scan architecture using SDSFF (State Dependent Scan Flip-Flop) against scan-based attack which achieves high security without compromising the testability is proposed. In SDSFF, there is a problem which is the update timing of the latch which added to the scan FF. In this paper, we propose the update timing to online test without sacrificing the security. In our method, the latches are updated by result which the value of KEY which decided when designed compared with any FFs in a scan chain. We show that by using proposed method, neither the secret key nor the testability of an RSA circuit implementation is compromised, and the effectiveness of the proposed method According the result, even with 100 SDSFFs, the introduced area overhead is 0.555% which less than the conventional method. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | scan chain / scan-based attack / secure scan architecture / RSA / SDSFF |
| Paper # | VLD2012-57,SIP2012-79,ICD2012-74,IE2012-81 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2012/10/11(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Secure Scan Architecture Using State Dependent Scan Flip-Flop with Key-Based Configuration on RSA Circuit |
| Sub Title (in English) | |
| Keyword(1) | scan chain |
| Keyword(2) | scan-based attack |
| Keyword(3) | secure scan architecture |
| Keyword(4) | RSA |
| Keyword(5) | SDSFF |
| 1st Author's Name | Yuta ATOBE |
| 1st Author's Affiliation | Grad. of Fundamental Science and Engineering, Waseda University() |
| 2nd Author's Name | Youhua SHI |
| 2nd Author's Affiliation | Waseda Institute for Advanced Study, Waseda University |
| 3rd Author's Name | Masao YANAGISAWA |
| 3rd Author's Affiliation | Grad. of Fundamental Science and Engineering, Waseda University |
| 4th Author's Name | Nozomu TOGAWA |
| 4th Author's Affiliation | Grad. of Fundamental Science and Engineering, Waseda University |
| Date | 2012-10-19 |
| Paper # | VLD2012-57,SIP2012-79,ICD2012-74,IE2012-81 |
| Volume (vol) | vol.112 |
| Number (no) | 247 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |