Presentation 2012-10-19
A Low Power CMOS Motion Estimation Processor Implementing Dynamic Voltage and Frequency Scaling (DVFS) and Adaptively Assigned Breaking-off Condition (A^2BC) Motion Estimation Algorithm
Tadayoshi Enomoto, Nobuaki Kobayashi,
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Abstract(in English) A motion estimation (ME) processor was developed by employing dynamic voltage and frequency scaling (DVFS) technique to greatly reduce the power dissipation. To make full use of the advantages of DVFS technique, a fast ME algorithm was also developed. It can adaptively predict the optimum supply voltage and the optimum clock frequency before ME process starts for each macro-block for encoding. Power dissipation of the 90-nm CMOS DVFS controlled ME processor, which contained an absolute difference accumulator as well as a small on-chip DC/DC level converter, a minimum value detector and DVFS controller, was reduced to 73.6μW, which was only 1.02% that of a conventional ME processor.
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Keyword(in English) power dissipation / H.264/AVC / motion estimation processor / DVFS / PLL clock driver
Paper # VLD2012-53,SIP2012-75,ICD2012-70,IE2012-77
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Conference Date 2012/10/11(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Low Power CMOS Motion Estimation Processor Implementing Dynamic Voltage and Frequency Scaling (DVFS) and Adaptively Assigned Breaking-off Condition (A^2BC) Motion Estimation Algorithm
Sub Title (in English)
Keyword(1) power dissipation
Keyword(2) H.264/AVC
Keyword(3) motion estimation processor
Keyword(4) DVFS
Keyword(5) PLL clock driver
1st Author's Name Tadayoshi Enomoto
1st Author's Affiliation Graduate School of Science and Engineering, Chuo University()
2nd Author's Name Nobuaki Kobayashi
2nd Author's Affiliation Graduate School of Science and Engineering, Chuo University
Date 2012-10-19
Paper # VLD2012-53,SIP2012-75,ICD2012-70,IE2012-77
Volume (vol) vol.112
Number (no) 247
Page pp.pp.-
#Pages 6
Date of Issue