Presentation 2012-10-19
CMOS Op-amp Circuit Synthesis with Geometric Programming
Yu ZHANG, Qing DONG, Shigetoshi NAKATAKE, Bo YANG, Jing LI,
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Abstract(in English) This work presents a 6T SRAM design in nanometer process via geometric programming (GP). We adopt the transistor array (TA) as a layout style, where each transistor is decomposed into a set of unit transistors. We describe the GP program analyzing the relationship between the static noise margin of SRAM and the layout-dependent effects, and tackle to simultaneously optimize transistor sizes and the placement. As a result, we successfully generated the SRAM macro layout pattern with optimal transistor size and the finger number of each transistor.
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Keyword(in English) SRAM / Geometric Programming / Layout-dependent Effect / STI / WPE / TA
Paper # VLD2012-54,SIP2012-76,ICD2012-71,IE2012-78
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Committee VLD
Conference Date 2012/10/11(1days)
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Registration To VLSI Design Technologies (VLD)
Language ENG
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) CMOS Op-amp Circuit Synthesis with Geometric Programming
Sub Title (in English)
Keyword(1) SRAM
Keyword(2) Geometric Programming
Keyword(3) Layout-dependent Effect
Keyword(4) STI
Keyword(5) WPE
Keyword(6) TA
1st Author's Name Yu ZHANG
1st Author's Affiliation School of Environmental Engineering, The University of Kitakyushu()
2nd Author's Name Qing DONG
2nd Author's Affiliation Department of Information and Media Engineering, the University of Kitakyushu
3rd Author's Name Shigetoshi NAKATAKE
3rd Author's Affiliation Department of Information and Media Engineering, the University of Kitakyushu
4th Author's Name Bo YANG
4th Author's Affiliation Design Algorithm Laboratory, Inc.
5th Author's Name Jing LI
5th Author's Affiliation Design Algorithm Laboratory, Inc.
Date 2012-10-19
Paper # VLD2012-54,SIP2012-76,ICD2012-71,IE2012-78
Volume (vol) vol.112
Number (no) 245
Page pp.pp.-
#Pages 6
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