Presentation	2012-10-19 A 9-bit 10MSps SAR ADC with Double Input Range for Supply Voltage Gong CHEN, Yu ZHANG, Qing DONG, Shigetoshi NAKATAKE, Bo YANG, Jing LI,
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Abstract(in English)	This paper presents a pre-charge V_-based method for 1.2V 9-bit 10MSps Successive Approximation Register (SAR) ADC. This conversion mechanism achieves the twice range of the input signal range beyond the supply voltage. We introduces a dynamic comparator with a special design and an additional comparison stage before each redistribution stage in the pre-conversion. The prototype was designed on 65nm CMOS technology. The simulation results shows INL and DNL 0.05 and 0.035LSB respectively. The ADC consumes a total energy of 0.504mW at a 1.2V supply and 10MSps.
Keyword(in Japanese)	(See Japanese page)
Keyword(in English)	SAR-ADC / Double Input Ranage
Paper #	VLD2012-49,SIP2012-71,ICD2012-66,IE2012-73
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Committee	VLD
Conference Date	2012/10/11(1days)
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Paper Information
Registration To	VLSI Design Technologies (VLD)
Language	ENG
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	A 9-bit 10MSps SAR ADC with Double Input Range for Supply Voltage
Sub Title (in English)
Keyword(1)	SAR-ADC
Keyword(2)	Double Input Ranage
1st Author's Name	Gong CHEN
1st Author's Affiliation	School of Environmental Engineering, The University of Kitakyusyu()
2nd Author's Name	Yu ZHANG
2nd Author's Affiliation	School of Environmental Engineering, The University of Kitakyusyu
3rd Author's Name	Qing DONG
3rd Author's Affiliation	School of Environmental Engineering, The University of Kitakyusyu
4th Author's Name	Shigetoshi NAKATAKE
4th Author's Affiliation	School of Environmental Engineering, The University of Kitakyusyu
5th Author's Name	Bo YANG
5th Author's Affiliation	Design Algorithm Labratory, Inc.
6th Author's Name	Jing LI
6th Author's Affiliation	Design Algorithm Labratory, Inc.
Date	2012-10-19
Paper #	VLD2012-49,SIP2012-71,ICD2012-66,IE2012-73
Volume (vol)	vol.112
Number (no)	245
Page	pp.pp.-
#Pages	5
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