| Presentation | 2012-10-19 Design of a Packet-Transfer-Based Dynamic Reconfigurable VLSI Processor for Reduction of a Configuration Memory Size Yoshichika FUJIOKA, Michitaka KAMEYAMA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Register-transfer-level packet routing scheme is proposed for intra-chip data transfer to make the size of configuration memory for dynamically reconfigurable VLSI processors greatly reduced. Configuration memory reduction in the conventional dynamically reconfigurable parallel VLSI processor can be achieved based on semi-autonomous packet routing, where both autonomous packet data transfer and offline scheduling/allocation are effectively utilized. It is demonstrated that we can make the control storage size much smaller than the conventional dynamically reconfigurable VLSI, even in the case where the CDFG contains many conditional branches. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | coarse-grain reconfigurable VLSI processor / semi-autonomous packet routing / configuration memory / conditional branches |
| Paper # | VLD2012-47,SIP2012-69,ICD2012-64,IE2012-71 |
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| Conference Information | |
| Committee | SIP |
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| Conference Date | 2012/10/11(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Signal Processing (SIP) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design of a Packet-Transfer-Based Dynamic Reconfigurable VLSI Processor for Reduction of a Configuration Memory Size |
| Sub Title (in English) | |
| Keyword(1) | coarse-grain reconfigurable VLSI processor |
| Keyword(2) | semi-autonomous packet routing |
| Keyword(3) | configuration memory |
| Keyword(4) | conditional branches |
| 1st Author's Name | Yoshichika FUJIOKA |
| 1st Author's Affiliation | Faculty of Engineering, Hachinohe Institute of Technology() |
| 2nd Author's Name | Michitaka KAMEYAMA |
| 2nd Author's Affiliation | Graduate School of Information Sciences, Tohoku University |
| Date | 2012-10-19 |
| Paper # | VLD2012-47,SIP2012-69,ICD2012-64,IE2012-71 |
| Volume (vol) | vol.112 |
| Number (no) | 246 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |