| Presentation | 2012-08-03 A 40nm Ultra Low Voltage SAR ADC with Timing Optimized Asynchronous Clock Generator Ryota SEKIMOTO, Akira SHIKATA, Kentaro YOSHIOKA, Tadahiro KURODA, Hiroki ISHIKURO, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper presents an ultra low power and low voltage successive approximation register (SAR) analog to digital converter (ADC) that uses an adaptive timing optimized asynchronous clock generator. By calibrating the delay time of the clock generator, the DAC settling time is optimized to counter the device mismatch. Test chip has been fabricated in 40nm standard CMOS process and achieved 7.5-ENOB (Effective Number of Bits) and figure of merit (FoM) of 8.75-J/conversion-step with 2.048MS/s. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | ultra low voltage / ultra low power / SAR / ADC |
| Paper # | SDM2012-88,ICD2012-56 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2012/7/26(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A 40nm Ultra Low Voltage SAR ADC with Timing Optimized Asynchronous Clock Generator |
| Sub Title (in English) | |
| Keyword(1) | ultra low voltage |
| Keyword(2) | ultra low power |
| Keyword(3) | SAR |
| Keyword(4) | ADC |
| 1st Author's Name | Ryota SEKIMOTO |
| 1st Author's Affiliation | Department of Electronics and Electrical Engineering, Keio University() |
| 2nd Author's Name | Akira SHIKATA |
| 2nd Author's Affiliation | Department of Electronics and Electrical Engineering, Keio University |
| 3rd Author's Name | Kentaro YOSHIOKA |
| 3rd Author's Affiliation | Department of Electronics and Electrical Engineering, Keio University |
| 4th Author's Name | Tadahiro KURODA |
| 4th Author's Affiliation | Department of Electronics and Electrical Engineering, Keio University |
| 5th Author's Name | Hiroki ISHIKURO |
| 5th Author's Affiliation | Department of Electronics and Electrical Engineering, Keio University |
| Date | 2012-08-03 |
| Paper # | SDM2012-88,ICD2012-56 |
| Volume (vol) | vol.112 |
| Number (no) | 170 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |