Presentation 2012-08-03
0.45-V Input Higher Than 90% Efficiency Buck Converter with On-Chip Gate Boost
Xin Zhang, Po-Hung Chen, Yoshikatsu Ryu, Koichi Ishida, Yasuyuki Okuma, Kazunori Watanabe, Takayasu Sakurai, Makoto Takamiya,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) A low input voltage buck converter with on-chip gate boost and digital PWM controller is proposed and fabricated in 40-nm CMOS process. The on-chip gate boost and clock gating technique are employed to achieve >90% efficiency for heavy load and light load, respectively.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Buck Converter / On-Chip Gate Boost / Power Management
Paper # SDM2012-83,ICD2012-51
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Committee ICD
Conference Date 2012/7/26(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language ENG
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) 0.45-V Input Higher Than 90% Efficiency Buck Converter with On-Chip Gate Boost
Sub Title (in English)
Keyword(1) Buck Converter
Keyword(2) On-Chip Gate Boost
Keyword(3) Power Management
1st Author's Name Xin Zhang
1st Author's Affiliation University of Tokyo()
2nd Author's Name Po-Hung Chen
2nd Author's Affiliation University of Tokyo
3rd Author's Name Yoshikatsu Ryu
3rd Author's Affiliation Semiconductor Technology Academic Research Center (STARC)
4th Author's Name Koichi Ishida
4th Author's Affiliation University of Tokyo
5th Author's Name Yasuyuki Okuma
5th Author's Affiliation Semiconductor Technology Academic Research Center (STARC)
6th Author's Name Kazunori Watanabe
6th Author's Affiliation Semiconductor Technology Academic Research Center (STARC)
7th Author's Name Takayasu Sakurai
7th Author's Affiliation University of Tokyo
8th Author's Name Makoto Takamiya
8th Author's Affiliation University of Tokyo
Date 2012-08-03
Paper # SDM2012-83,ICD2012-51
Volume (vol) vol.112
Number (no) 170
Page pp.pp.-
#Pages 4
Date of Issue