Presentation	2012-08-03 Design of system LSI/memory with low power tunneling type transistor Ryosuke SUZUKI, Shigeyoshi WATANABE,
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Abstract(in English)	Design method of system LSI such as inverter, NAND, and full adder with low power tunnel transistor has been described. Pattern area of system LSI with plane tunnel transistor is larger than that with conventional planar CMOS transistor. By introducing FinFET type tunnel transistor pattern area of system LSI can be reduced to smaller value compared with that using conventional planar CMOS transistor. Moreover, the new low electric power DRAM memory cell using a SEA cell was newly examined.
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Keyword(in English)	Low power / tunnel type transistor / pattern layout / system LSI
Paper #	SDM2012-77,ICD2012-45
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Conference Information
Committee	ICD
Conference Date	2012/7/26(1days)
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Paper Information
Registration To	Integrated Circuits and Devices (ICD)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	Design of system LSI/memory with low power tunneling type transistor
Sub Title (in English)
Keyword(1)	Low power
Keyword(2)	tunnel type transistor
Keyword(3)	pattern layout
Keyword(4)	system LSI
1st Author's Name	Ryosuke SUZUKI
1st Author's Affiliation	Graduate School of Electrical and Information Engineering, Shonan Institute of Technology()
2nd Author's Name	Shigeyoshi WATANABE
2nd Author's Affiliation	Graduate School of Electrical and Information Engineering, Shonan Institute of Technology
Date	2012-08-03
Paper #	SDM2012-77,ICD2012-45
Volume (vol)	vol.112
Number (no)	170
Page	pp.pp.-
#Pages	5
Date of Issue