| Presentation | 2012-08-02 Design Technology of stacked Type Chain PRAM Readout Sho KATO, Shigeyoshi WATANABE, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Stacked type chain PRAM which enables to realize lower cost than NAND flash memory has been newly proposed. Cell structure, core circuit, and the design method for realizing stable read and write operation for the stacked type chain PRAM have been described. The newly proposed stacked type chain PRAM is apromising candidate for realizing high-speed, low-cost, future non-volatile semiconductor memory. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Non-volatile memory / PRAM / phase change material / Chain structure |
| Paper # | SDM2012-76,ICD2012-44 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2012/7/26(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Vice Chair | |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design Technology of stacked Type Chain PRAM Readout |
| Sub Title (in English) | |
| Keyword(1) | Non-volatile memory |
| Keyword(2) | PRAM |
| Keyword(3) | phase change material |
| Keyword(4) | Chain structure |
| 1st Author's Name | Sho KATO |
| 1st Author's Affiliation | Department of Information Science, Shonan Institute of Technology() |
| 2nd Author's Name | Shigeyoshi WATANABE |
| 2nd Author's Affiliation | Department of Information Science, Shonan Institute of Technology |
| Date | 2012-08-02 |
| Paper # | SDM2012-76,ICD2012-44 |
| Volume (vol) | vol.112 |
| Number (no) | 170 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |