Presentation	2012-08-02 Self-Improvement of Cell Stability in SRAM by Post Fabrication Technique Anil Kumar, MIYANO Shinji /, Toshiro HIRAMOTO,
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Abstract(in English)	The post fabrication technique for self-improvement of SRAM cell stability is validated by experiment using 1k DMA SRAM TEG array. It is shown that the stability of unbalance cells is automatically improved by merely applying stress voltage to V_ terminal. The mechanism of the phenomena is also analyzed by measuring V_	of all transistors before and after stress and it is newly found that |V_	| of the weaker PFET connected to the LOW node in the cell is selectively lowered by the self-improve mechanism and this |V_	| shift largely contributes to the self-improvement.
Keyword(in Japanese)	(See Japanese page)
Keyword(in English)	Threshold Voltage / CMOS / SRAM
Paper #	SDM2012-65,ICD2012-33
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Conference Information
Committee	ICD
Conference Date	2012/7/26(1days)
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Paper Information
Registration To	Integrated Circuits and Devices (ICD)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	Self-Improvement of Cell Stability in SRAM by Post Fabrication Technique
Sub Title (in English)
Keyword(1)	Threshold Voltage
Keyword(2)	CMOS
Keyword(3)	SRAM
1st Author's Name	Anil Kumar
1st Author's Affiliation	Institute of Industrial Science, University of Tokyo()
2nd Author's Name	MIYANO Shinji /
2nd Author's Affiliation	Institute of Industrial Science, University of Tokyo
3rd Author's Name	Toshiro HIRAMOTO
3rd Author's Affiliation	STARC
Date	2012-08-02
Paper #	SDM2012-65,ICD2012-33
Volume (vol)	vol.112
Number (no)	170
Page	pp.pp.-
#Pages	4
Date of Issue