| Presentation | 2012-08-02 A 40-nm 256-Kb Sub-10 pJ/Access 8T SRAM with Read Bitline Amplitude Limiting (RBAL) Scheme Shusuke YOSHIMOTO, Masaharu TERADA, Youhei UMEKI, Shunsuke OKUMURA, Atsushi KAWASUMI, Toshikazu SUZUKI, Shinichi MORIWAKI, Shinji MIYANO, Hiroshi KAWAGUCHI, Masahiko YOSHIMOTO, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper presents a novel read-bitline amplitude limiting (RBAL) scheme which suppresses dynamic energy dissipation caused by random variation. In addition, a discharge acceleration (DA) circuit is proposed to decrease delay overhead of RBAL. The proposed scheme improves the active energy dissipation in a read cycle by 22% at the center-center (CC) corner and 25℃. The maximum delay overhead is 32% at the fast-slow (FS) corner and -40℃. The circuits have been implemented using the 40-nm bulk CMOS process. The implemented 256-Kb 8T SRAM works fine with energy dissipation of sub-10 pJ / access from 0.5-0.7V. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | 8T SRAM / low voltage / low energy / read bitline limiter / discharge accelerator |
| Paper # | SDM2012-64,ICD2012-32 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2012/7/26(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A 40-nm 256-Kb Sub-10 pJ/Access 8T SRAM with Read Bitline Amplitude Limiting (RBAL) Scheme |
| Sub Title (in English) | |
| Keyword(1) | 8T SRAM |
| Keyword(2) | low voltage |
| Keyword(3) | low energy |
| Keyword(4) | read bitline limiter |
| Keyword(5) | discharge accelerator |
| 1st Author's Name | Shusuke YOSHIMOTO |
| 1st Author's Affiliation | Graduate School of System Informatics, Kobe University() |
| 2nd Author's Name | Masaharu TERADA |
| 2nd Author's Affiliation | Graduate School of System Informatics, Kobe University |
| 3rd Author's Name | Youhei UMEKI |
| 3rd Author's Affiliation | Graduate School of System Informatics, Kobe University |
| 4th Author's Name | Shunsuke OKUMURA |
| 4th Author's Affiliation | Graduate School of System Informatics, Kobe University |
| 5th Author's Name | Atsushi KAWASUMI |
| 5th Author's Affiliation | Semiconductor Technology Academic Research Center (STARC) |
| 6th Author's Name | Toshikazu SUZUKI |
| 6th Author's Affiliation | Semiconductor Technology Academic Research Center (STARC) |
| 7th Author's Name | Shinichi MORIWAKI |
| 7th Author's Affiliation | Semiconductor Technology Academic Research Center (STARC) |
| 8th Author's Name | Shinji MIYANO |
| 8th Author's Affiliation | Semiconductor Technology Academic Research Center (STARC) |
| 9th Author's Name | Hiroshi KAWAGUCHI |
| 9th Author's Affiliation | Graduate School of System Informatics, Kobe University |
| 10th Author's Name | Masahiko YOSHIMOTO |
| 10th Author's Affiliation | Graduate School of System Informatics, Kobe University |
| Date | 2012-08-02 |
| Paper # | SDM2012-64,ICD2012-32 |
| Volume (vol) | vol.112 |
| Number (no) | 170 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |