| Presentation | 2012-07-27 Loop Design Optimization for Fourth-Order Fractional-N PLL Frequency Synthesizers Shoichi MASUI, Jun Gyu LEE, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We propose a methodology of loop design optimization for fourth-order fractional-N PLL frequency synthesizers featuring a settling time of 5μsec for applications such as an automobile smart-key systems. The optimized design flow overcomes the inaccuracy to derive the relationship between the settling time and loop bandwidth in the fourth-order PLL by using MATLAB Control System Toolbox and features the worst-case design against the process, voltage and temperature (PVT) variations in the loop filter components. Also the tradeoff between the phase noise and area is considered. The optimization process consists of 1) derivation of the accurate relationship between the settling time and loop bandwidth for various PVT conditions, 2) derivation of phase noise and area as a function of an area-dominant filter capacitance, and 3) derivation of all loop filter components. The optimized design result is verified with circuit simulations and experimental results designed in a 1.8V 0.18μm CMOS technology. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | phase locked loop / frequency synthesizer / loop design |
| Paper # | ICD2012-27 |
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| Committee | ICD |
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| Conference Date | 2012/7/19(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Loop Design Optimization for Fourth-Order Fractional-N PLL Frequency Synthesizers |
| Sub Title (in English) | |
| Keyword(1) | phase locked loop |
| Keyword(2) | frequency synthesizer |
| Keyword(3) | loop design |
| 1st Author's Name | Shoichi MASUI |
| 1st Author's Affiliation | Fujitsu Laboratories() |
| 2nd Author's Name | Jun Gyu LEE |
| 2nd Author's Affiliation | Tohoku University |
| Date | 2012-07-27 |
| Paper # | ICD2012-27 |
| Volume (vol) | vol.112 |
| Number (no) | 159 |
| Page | pp.pp.- |
| #Pages | 6 |
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