Presentation 2012-07-19
Design of a 2bit Bit-Slice Half-Precision Floating-Point Multiplier Using SFQ Circuits
Yohei NARUSE, Nobutaka KITO, Naofumi TAKAGI,
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Abstract(in English) Single flux quantum (SFQ) circuits are expected as next-generation circuits. Arithmetic circuits using SFQ circuits have been designed based on bit-serial structure. When the bit width of input data increases, the number of cycles for input data increases. In this report, we propose a floating-point multiplier operating based on bit-slice architecture. We design a 2bit bit-slice floating-point multiplier and bit-serial floating-point multiplier at gate level and conpare the performances of them respectively. We design a 2bit bit-slice half-precision floating-point multiplier. The number of junctions and delay time are 50531 and 7849ps.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) SFQ circuit / Single Flux Quantum circuit / multiplier / bit-slice / floating-point multiplier
Paper # SCE2012-12
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Committee SCE
Conference Date 2012/7/12(1days)
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Registration To Superconductive Electronics (SCE)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Design of a 2bit Bit-Slice Half-Precision Floating-Point Multiplier Using SFQ Circuits
Sub Title (in English)
Keyword(1) SFQ circuit
Keyword(2) Single Flux Quantum circuit
Keyword(3) multiplier
Keyword(4) bit-slice
Keyword(5) floating-point multiplier
1st Author's Name Yohei NARUSE
1st Author's Affiliation Kyoto University Engineering Department()
2nd Author's Name Nobutaka KITO
2nd Author's Affiliation Chukyo University
3rd Author's Name Naofumi TAKAGI
3rd Author's Affiliation Kyoto University Engineering Department
Date 2012-07-19
Paper # SCE2012-12
Volume (vol) vol.112
Number (no) 138
Page pp.pp.-
#Pages 5
Date of Issue