Presentation 2012-07-19
SFQ Bit-Slice Floating Point Adder
Yukio OHMOMO, Yohei NARUSE, Nobutaka KITO, Naofumi TAKAGI, Kazuyoshi TAKAGI,
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Abstract(in English) Single Flux Quantum (SFQ) circuits operate at high-speed with low-power consumption. A Large-Scale Reconfigurable Data Path (LSRDP) is proposed as an accelerator of a high-performance computer. The previously proposed floating-point arithmetic units (FPUs) for SFQ-LSRDP are based on the bit-serial architecture. For accomplishing an operation on long-bit data, bit-serial FPUs take a lot of clock cycles, and their throughputs are low. In this report, we propose bit-slice floating-point adders (FPAs). For a k-bit bit-slice FPA, we employ a radix-2^k floating-point number format. Compared to the bit-serial FPA, a k-bit bit-slice FPA takes about 1/k number clock cycles with slightly larger hardware, and its throughput is expected to be k times higher.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) SFQ Circuit / Floating Point Adder / Bit-Slice
Paper # SCE2012-11
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Conference Information
Committee SCE
Conference Date 2012/7/12(1days)
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Paper Information
Registration To Superconductive Electronics (SCE)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) SFQ Bit-Slice Floating Point Adder
Sub Title (in English)
Keyword(1) SFQ Circuit
Keyword(2) Floating Point Adder
Keyword(3) Bit-Slice
1st Author's Name Yukio OHMOMO
1st Author's Affiliation Kyoto University()
2nd Author's Name Yohei NARUSE
2nd Author's Affiliation Kyoto University
3rd Author's Name Nobutaka KITO
3rd Author's Affiliation Chukyo University
4th Author's Name Naofumi TAKAGI
4th Author's Affiliation Kyoto University
5th Author's Name Kazuyoshi TAKAGI
5th Author's Affiliation Kyoto University
Date 2012-07-19
Paper # SCE2012-11
Volume (vol) vol.112
Number (no) 138
Page pp.pp.-
#Pages 5
Date of Issue