Presentation | 2012-07-03 Secure Scan Architecture on RSA Circuit Using State Dependent Scan Flip Flop against Scan-Based Side Channel Attack Yuta ATOBE, Youhua SHI, Masao YANAGISAWA, Nozomu TOGAWA, |
---|---|
PDF Download Page | PDF download Page Link |
Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | Scan test that is one of the useful design for testability tecniques, which can control and observe the FFs(Flip Flops) inside LSIs, can detect circuit failure efficiently. On the other hand, a scan-based attack using scan chain which retrieves secret keys of cryptographic LSIs is considered. Generaly testability and security are contradictory, there is a need for an efficient design for testability circuit to satisfy both testability and security. In this paper, a secure scan architecture against scan-based attack which have high testability is proposed. In our method, scan data is state-dependent changed unintelligible data to attackers by adding the latch to any FFs in the scan chain. Changing the value of the FFs can dynamically change the scan data. The tester can test as a normal scan test because they know the structure of the extended circuit. We made an analysis on an RSA implementation to show the effectiveness of the proposed method and discussed how our approach is resistant to scan-based attack. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | scan chain / scan-based attack / secure scan architecture / RSA |
Paper # | CAS2012-21,VLD2012-31,SIP2012-53,MSS2012-21 |
Date of Issue |
Conference Information | |
Committee | MSS |
---|---|
Conference Date | 2012/6/25(1days) |
Place (in Japanese) | (See Japanese page) |
Place (in English) | |
Topics (in Japanese) | (See Japanese page) |
Topics (in English) | |
Chair | |
Vice Chair | |
Secretary | |
Assistant |
Paper Information | |
Registration To | Mathematical Systems Science and its applications(MSS) |
---|---|
Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Secure Scan Architecture on RSA Circuit Using State Dependent Scan Flip Flop against Scan-Based Side Channel Attack |
Sub Title (in English) | |
Keyword(1) | scan chain |
Keyword(2) | scan-based attack |
Keyword(3) | secure scan architecture |
Keyword(4) | RSA |
1st Author's Name | Yuta ATOBE |
1st Author's Affiliation | Grad. of Fundamental Science and Engineering, Waseda University() |
2nd Author's Name | Youhua SHI |
2nd Author's Affiliation | Waseda Institute for Advanced Study, Waseda University |
3rd Author's Name | Masao YANAGISAWA |
3rd Author's Affiliation | Grad. of Fundamental Science and Engineering, Waseda University |
4th Author's Name | Nozomu TOGAWA |
4th Author's Affiliation | Grad. of Fundamental Science and Engineering, Waseda University |
Date | 2012-07-03 |
Paper # | CAS2012-21,VLD2012-31,SIP2012-53,MSS2012-21 |
Volume (vol) | vol.112 |
Number (no) | 116 |
Page | pp.pp.- |
#Pages | 6 |
Date of Issue |