Presentation 2012-07-02
An Evaluation of Heuristic Fault Simulation Algorithms for Transient Faults in Sequential Circuits
Taiga TAKATA, Masayoshi YOSHIMURA, Yusuke MATSUNAGA,
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Abstract(in English) The number of hard errors which can be assumed in a sequential circuit is proportional to the circuit size, since it corresponds to the number of locations where an error occurs. On the other hand, the number of soft errors which can be assumed in a sequential circuit can be much larger, since it corresponds to the number of locations multiplied by the number of clock cycles when an error occurs. Fault simulation for analyzing soft error propagations in a large-scale sequential circuit might consume large run-time due to the large number of errors. This paper shows several heuristics for accelerating fault simulation for analyzing soft error propagations. The heuristics are experimentally evaluated.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Soft error / sequential circuits / fault simulation
Paper # CAS2012-10,VLD2012-20,SIP2012-42,MSS2012-10
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Conference Date 2012/6/25(1days)
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Registration To Mathematical Systems Science and its applications(MSS)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) An Evaluation of Heuristic Fault Simulation Algorithms for Transient Faults in Sequential Circuits
Sub Title (in English)
Keyword(1) Soft error
Keyword(2) sequential circuits
Keyword(3) fault simulation
1st Author's Name Taiga TAKATA
1st Author's Affiliation Faculty of Information Science and Electrical Engineering, Kyushu University()
2nd Author's Name Masayoshi YOSHIMURA
2nd Author's Affiliation Faculty of Information Science and Electrical Engineering, Kyushu University
3rd Author's Name Yusuke MATSUNAGA
3rd Author's Affiliation Faculty of Information Science and Electrical Engineering, Kyushu University
Date 2012-07-02
Paper # CAS2012-10,VLD2012-20,SIP2012-42,MSS2012-10
Volume (vol) vol.112
Number (no) 116
Page pp.pp.-
#Pages 6
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