Presentation | 2012-03-02 Design and Implementation of I/O Control Mechanism for Heterogeneous Multi-Core Processors Yuki KAWAGUCHI, Kazutoshi SUITO, Hiroki MATSUTANI, Nobuyuki YAMASAKI, |
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Abstract(in English) | Heterogeneous multi-core architecture that consists of processors, memory modules, and I/O devices with various sizes, functions, and speeds is one of attractive solutions for embedded systems. In particular, a control mechanism that supports low-latency and high-throughput I/O processing is required for various I/O devices on the heterogeneous multi-core processors. In this paper, we design and implement a dedicated I/O processor for heterogeneous multi-core architecture with various I/O devices. The dedicated I/O core has a hardware mechanism which is in charge of efficient I/O request management and communication with I/O devices. Evaluation results show that the dedicated I/O core improves the I/O access latency and throughput compared with software-based I/O processing. |
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Paper # | CPSY2011-85,DC2011-89 |
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Committee | DC |
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Conference Date | 2012/2/24(1days) |
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Registration To | Dependable Computing (DC) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
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Title (in English) | Design and Implementation of I/O Control Mechanism for Heterogeneous Multi-Core Processors |
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1st Author's Name | Yuki KAWAGUCHI |
1st Author's Affiliation | Faculty of Science and Technology, Keio University() |
2nd Author's Name | Kazutoshi SUITO |
2nd Author's Affiliation | Faculty of Science and Technology, Keio University |
3rd Author's Name | Hiroki MATSUTANI |
3rd Author's Affiliation | Faculty of Science and Technology, Keio University |
4th Author's Name | Nobuyuki YAMASAKI |
4th Author's Affiliation | Faculty of Science and Technology, Keio University |
Date | 2012-03-02 |
Paper # | CPSY2011-85,DC2011-89 |
Volume (vol) | vol.111 |
Number (no) | 462 |
Page | pp.pp.- |
#Pages | 6 |
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