Presentation 2012-03-02
Design and Implementation of Distributed TLB Mechanism for Heterogeneous Multi-Core Processors
Daiki KAWASE, Kazutoshi SUITO, Hiroki MATSUTANI, Nobuyuki YAMASAKI,
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Abstract(in English) Heterogeneous multi-core architecture, in which processor cores, memory modules, and I/O modules with various sizes, functions, and speeds are interconnected via Network-on-Chip (NoC), is one of attractive solutions for embedded systems customized for a given application set. In this paper, we propose a distributed TLB (Translation-Lookaside Buffer) mechanism for efficient memory management on the heterogeneous multi-core processors. Specifically, small-sized level-1 TLBs dedicated to each processor core and a single large-sized level-2 TLB shared by all processor cores are implemented on a chip. The level-2 TLB is accessed only when a level-1 TLB miss is incurred. Performance, area, and power of the distributed TLB mechanism can be further optimized by adjusting entry sizes of level-1 TLBs. Preliminary evaluation results show that the distributed TLB mechanism can reduce the area and power compared to single-level flat TLB architecture.
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Paper # CPSY2011-84,DC2011-88
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Committee DC
Conference Date 2012/2/24(1days)
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Language JPN
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Title (in English) Design and Implementation of Distributed TLB Mechanism for Heterogeneous Multi-Core Processors
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1st Author's Name Daiki KAWASE
1st Author's Affiliation Faculty of Science and Technology, Keio University()
2nd Author's Name Kazutoshi SUITO
2nd Author's Affiliation Faculty of Science and Technology, Keio University
3rd Author's Name Hiroki MATSUTANI
3rd Author's Affiliation Faculty of Science and Technology, Keio University
4th Author's Name Nobuyuki YAMASAKI
4th Author's Affiliation Faculty of Science and Technology, Keio University
Date 2012-03-02
Paper # CPSY2011-84,DC2011-88
Volume (vol) vol.111
Number (no) 462
Page pp.pp.-
#Pages 6
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